Md. Abu Sayed Chowdhury
Lecturer, Department of EEE, BRAC University
B.Sc. in EEE, Bangladesh University of Engineering and Technology (BUET)
I work on in-memory logic in memristor crossbars: storing each weight in two devices, then programming and reading them with ordinary 45 nm CMOS. I'm applying to PhD programs in this area for Fall 2027.
First-author paper at IEEE EDTM 2026 in Penang, Malaysia. B.Sc. CGPA 3.95/4.00, ranked 7th of 213. Currently pursuing an M.Sc. at BUET.
Research interests
In-memory computing
Memristor/ReRAM crossbars and hybrid memristor-CMOS circuits that compute Boolean and arithmetic functions where the data is stored, cutting data movement.
Neuromorphic hardware
Spiking neural hardware, memristor synapses, and low-latency accelerators for edge AI.
Low-power peripheral circuits
The CMOS around the array: programming drivers, sense amplifiers, and low-power ADC/DAC readout, which often set a crossbar's real energy and area cost.
What I want to work on next
My thesis showed that binary-neural-network-style weights in a crossbar can compute any Boolean function in simulation. The open questions are what happens with real devices and at scale. In a PhD I want to study how device variability, limited endurance, and wire resistance affect in-memory logic and inference, and design circuits and mapping schemes that tolerate them. I'm also interested in moving from single gates to multi-bit arithmetic and full layers running in one array.
Publications
In-Memory Boolean Logic Computation in Binary Neural Network Inspired Memristor Crossbar Array
M. A. S. Chowdhury and O. Hassan. 10th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Penang, Malaysia, 2026, pp. 1–3. Poster presented on March 3, 2026.
© 2026 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses. The final published version is available at the DOI above.
Abstract
Neural network hardware is often implemented using memristor crossbars for their non-volatility, high density, and parallel computation capability. This work presents a methodology for implementing single-bit logic computation within such memory array structures, using a binary neural network approach to design the gates. Each binary weight is encoded with two memristor devices, and standard CMOS drivers handle programming and readout. Circuit-level SPICE simulations show NAND and XOR gates working, and cascading them gives a working full adder. Any Boolean function can be implemented with this methodology.
How a NAND gate works in the array
The weights for a 2-input NAND are [−1, −1] with a bias of +1. Each weight becomes a pair of memristors: −1 is (high, low) and +1 is (low, high). Switch the inputs to see which cells conduct and how the comparator decides the output.
| Row | Input | Weight | Col Y1 | Col Y2 |
|---|
low resistance (1) high resistance (0). Logic 1 is +0.8 V, logic 0 is −0.8 V, and the bias input is always 1.
| A | B | Y |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
- Memristors are programmed row by row with a half-bias scheme. A cell is set with 0 V on its wordline and 1.6 V on its bitline, and reset with the reverse. Unselected lines sit at 0.8 V, so half-selected cells see at most 0.8 V and keep their state.
- In simulation, programming takes the first 12 ns. Computation starts at 20 ns, when the start signal rises to 1.1 V.
- XOR needs a hidden layer of two neurons. The full adder cascades two XOR circuits for the sum and uses a structure like the XOR hidden-output crossbar for the carry.
Education
M.Sc. in Electrical and Electronic Engineering
Bangladesh University of Engineering and Technology (BUET)
B.Sc. in Electrical and Electronic Engineering
Bangladesh University of Engineering and Technology (BUET)
- CGPA 3.95/4.00, class rank 7 of 213. Dean's List in every academic year.
- Coursework: VLSI Circuits and Design, Analog Integrated Circuits, Semiconductor and Nano Devices, Introduction to Nanotechnology and Nanoelectronics, Processing and Fabrication Technology, Privacy Preserving Machine Learning, Spintronics.
Experience
Lecturer
Department of EEE, BSRM School of Engineering, BRAC University
- Teaching Signals and Systems (EEE243), Numerical Techniques (EEE282), and Modeling and Simulation (EEE382).
Adjunct Lecturer
Department of EEE, BUET
- Ran lab sections for Electrical Circuits, Numerical Techniques, and Digital Signal Processing: pre-lab briefings, demonstrations, and help debugging experiments.
- Helped update the lab curriculum and assessments. Gave students feedback and mentoring.
Undergraduate thesis researcher
In-memory logic implementation in memristor-based crossbar arrays, BUET. Supervisor: Dr. Orchi Hassan
- Developed an in-memory Boolean logic scheme modeled on binary neural networks; each binary weight is stored in two memristors in a crossbar array.
- Designed the CMOS programming and readout circuits in Cadence Virtuoso (GPDK045). SPICE simulations showed NAND and XOR gates and a cascaded full adder.
- Wrote and calibrated Verilog-A models based on VTEAM (threshold switching, nonlinear current–voltage behavior) for CMOS-memristor co-simulation.
Selected projects
16-bit carry skip adder: RTL to GDSII
SystemVerilog, Cadence Genus and Innovus, GPDK045. Dec 2024
- Designed a block-based adder with propagate/generate logic and 2:1 multiplexers that skip ripple-carry blocks.
- Wrote a layered SystemVerilog testbench with constrained-random stimulus. Coverage reached 100% on eight signed-arithmetic flag scenarios (Negative, Zero, Carry, Overflow).
- Synthesized block sizes k = 2, 4, 8 and compared power, delay, and area, then picked k = 4.
- Took the design through floorplanning, power mesh, placement, clock-tree synthesis, and routing in Innovus. The exported GDSII passed DRC/LVS with no setup or hold violations.
Analog 8:1 multiplexer for biomedical signal acquisition
Cadence Virtuoso, GPDK045, CMOS transmission gates. Feb 2024
- Designed for ECG and EEG acquisition: 24 CMOS transmission gates, eight input channels, three select lines.
- Characterized transient, AC, DC, and noise behavior at a 3 V supply.
- Sized the transistors against GPDK045 models to reduce crosstalk and signal distortion.
FPGA-based intelligent home automation
Verilog, Intel Quartus, Altera Flex EPF10K70. Aug 2023
- Wrote Verilog state machines that track people entering and leaving and switch the lights on when the room is occupied. The lights shut off automatically after 10 seconds.
- Used two infrared sensors for occupancy and NTC thermistors for temperature; the fan turns on above 30°C.
- Built four-speed PWM fan control with duty cycle set by occupancy: 1–3 people at 25%, 4–5 at 50%, 6–7 at 75%, 8–9 at 100%.
Skills and awards
IC design and EDA
- Cadence Virtuoso (schematic and layout)
- Genus (synthesis)
- Innovus (place-and-route, CTS)
- GPDK045, DRC/LVS
Hardware description and modeling
- Verilog, SystemVerilog, Verilog-A
- VTEAM memristor modeling
- RTL verification, functional coverage
- FSMs, FPGA with Intel Quartus Prime
Simulation and programming
- SPICE, LTspice, PSpice, Proteus
- Python (NumPy, pandas, PyTorch)
- MATLAB and Simulink
- C/C++, ARM assembly
Embedded platforms
- STM32
- Arduino
- ESP8266 and ESP32
- Altera FPGAs
First runner-up, VLSITHON 2024
University-wide VLSI design competition organized by Neural Semiconductor with BUET EEE Day 2024.
University Merit Scholarship, BUET
Awarded for academic excellence.
Contact
My CV has the full academic history and my referees. Email is the quickest way to reach me.